mode-locking frequency doubler是什么意思

网络释义

用法例句

4 GHz CMOS injection-locked frequency doubler,focusing on the theory analysis of locking range and phase noise performance of the frequency doubler.

4GHz CMOS注入锁频倍频器的设计和实现。

The phase jitter of output signal of the PLL( phase locked loop) frequency doubler is analyzed.

定量分析了数字式锁相倍频器输出信号的相位抖动.

A PLL Frequency Synthesizer with High Multiple-Frequency

一种多倍频选择的高倍频锁相环频率合成器

The Improvement of Thyristor Power Supply Device Based on Synchronous Circuit of Phase Locked Loop and Frequency Multiplier;

基于锁相环倍频同步电路的电源改进

New Frequency Track Technology Based on Multi-cycle Synchronization and Frequency Multiplication Phase-lock

新型多周期同步和倍频锁相的频率跟踪技术

Study on Active Mode-locking Intra-cavity Doubling Nd:YAG Green Light Laser;

主动锁模腔内倍频Nd：YAG绿光激光器的研究

Analysis and Application Design of RF PLL Frequency Synthesizer;

射频锁相环频率合成器的分析与设计

Study of Fractional-N Digital Phase Locked Loop Frequency Synthesizer;

分数分频数字锁相频率合成器的研究

Research of Fast Lock-in RF PLL Frequency Synthesizers;

宽带锁相式频率合成器快速锁定模式研究

automatic source-locking microwave frequency counter

自动微波锁相频率计数器

Modeling, Design and Implementation of Phase-locked Loop Frequency Synthesizer;

锁相环频率合成器建模、设计与实现

Analysis and Design of RF Oscillator and PLL Architecture;

射频振荡器与锁相环结构分析与设计

Design of PLL Frequency Synthesizer Based on CMOS Techniques;

基于CMOS工艺的锁相环频率合成器设计

Design of CMOS Integrated Phase-Locked Loop Frequency Synthesizer;

CMOS集成锁相式频率合成器设计

Design of a Fully Differential 1GHz CMOS PLL Frequency Synthesizer;

全差分1GHzCMOS锁相环频率综合器设计

Design of Digital Phase locked Frequency Synthesize Based on TC9181;

基于TC9181的数字锁相频率合成器的设计

Designing a Pulse-swallow PLL Freq. Synthesizer by using MC145152-2;

利用MC145152-2设计吞脉冲锁相频率合成器

Design of a Charge Pump Phase-Locked Loop for Frequency Synthesizer

用于频率合成器的电荷泵锁相环设计

Study of improving phase noise in thePLL based on PLL frequency synthesizer

基于PLL频率合成器锁相环的降噪技术